With development of semiconductor technology, feature size of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) decreases continuously. The reduced size of the MOSFET may cause a current leakage problem. Physical thickness of a gate dielectric layer can be increased without changing Equivalent Oxide Thickness (EOT) by use of a high-K gate dielectric layer, so as to reduce tunneling leakage current. However, a conventional poly-silicon gate is incompatible with the high-K gate dielectric layer. Depletion effect of the polysilicon gate can be avoided by using a metal gate together with the high-K gate dielectric layer. Meanwhile, gate resistance can be reduced and boron penetration can be avoided, thereby increasing reliability of the device. Consequently, combination of the metal gate and the high-K gate dielectric layer is widely used in the MOSFET. However, the combination of the metal gate and the high-K gate dielectric layer still faces various challenges, such as thermal stability problem and interface state problem. In particular, it is difficult for the MOSFET comprising the metal gate and the high-K gate dielectric layer to achieve a properly low threshold voltage due to Fermi pinning effect.
In order to achieve a proper threshold voltage, a P-type MOSFET should have an effective work function near the top of valence band of Si (about 5.2 eV). For the P-type MOSFET, a desired threshold voltage can be achieved by selecting a proper combination of the metal gate and the high-K gate dielectric layer. However, it is difficult to achieve such a high effective work function merely by selection of materials.